Non-volatile memory with resistive access component

ABSTRACT

Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.

BACKGROUND

Computers and other electronic products, e.g., digital televisions,digital cameras, and cellular phones, usually have a memory device withnumerous memory cells to store data and other information. Someconventional memory devices may store information based on the amount ofcharges on a storage node of the memory cell. Different values of thecharge on the storage node may represent different values (e.g., binaryvalues “0” and “1”) of the information stored in the memory cell. Thestorage node usually includes semiconductor material such as silicon.

Some other conventional memory devices, e.g., phase change memorydevices, may store information based on a resistance state (instead ofthe amount of charge) of a memory element of the memory cell. The memoryelement may include a phase change material, which may be written (e.g.,programmed) to change between different phases (e.g., crystalline andamorphous phases). Different phases of the material may cause the memorycell to have different resistance states to represent different valuesof the information stored in the memory cell.

The memory cell in these memory devices, e.g., phase change memorydevices, often includes an access component to allow access to thememory element. In some cases, the material of the access component andthe material of the memory element may have different processtemperature tolerances. Therefore, producing some conventional memorydevices may pose fabrication process challenges.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a memory device having a memory arraywith memory cells according to an embodiment of the invention.

FIG. 2 shows a partial block diagram of a memory device having a memoryarray including phase change memory cells with access components andmemory elements according to an embodiment of the invention.

FIG. 3 shows a cross-section of a memory cell with an ionic conductionpath according to an embodiment of the invention.

FIG. 4 is an example embodiment of current versus voltage (I-V)characteristics of an access component of the memory cell of FIG. 3.

FIG. 5 shows a cross-section of a memory cell including an accesscomponent having ionic-conducting chalcogenide material according to anembodiment of the invention.

FIG. 6 shows a cross-section of a memory cell including an accesscomponent having binary metal oxide material according to an embodimentof the invention.

FIG. 7 shows a cross-section of a memory cell including an accesscomponent having perovskite oxide material according to an embodiment ofthe invention.

FIG. 8 shows a partial schematic diagram of a memory device having amemory array according to an embodiment of the invention.

FIG. 9 shows a partial three-dimensional (3-D) view of a memory devicehaving memory cells located on a single device level according to anembodiment of the invention.

FIG. 10 shows a partial 3-D view of a memory device having memory cellsstacked on multiple device levels according to an embodiment of theinvention.

FIG. 11 shows a partial 3-D view of a memory device having memory cellsstacked on multiple device levels with shared conduction lines betweendevice levels according to an embodiment of the invention.

FIG. 12 through FIG. 17 show various processes of forming a memorydevice having memory cells according to an embodiment of the invention.

FIG. 18 and FIG. 19 show various processes of forming a memory devicehaving multiple device levels according to an embodiment of theinvention.

FIG. 20 through FIG. 24 show various processes of forming a memorydevice having multiple device levels with shared conduction linesaccording to an embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of a memory device 100 having a memoryarray 102 with memory cells 110 according to an embodiment of theinvention. Memory cells 110 may be arranged in rows and columns alongwith lines 123 (e.g., wordlines having signals Vx0 through VxM) andlines 124 (e.g., bit lines having signals Vy0 through VyN). Memorydevice 100 may use lines 123 and lines 124 to transfer informationwithin memory cells 110. Memory cells 110 may be physically located onmultiple device levels such that one group of memory cells 110 may bestacked on one or more groups of other memory cells 110. Row decoder 132and column decoder 134 may decode address signals A0 through AX on lines125 (e.g., address lines) to determine which memory cells 110 are to beaccessed. Row and column level decoders 136 and 138 of row and columndecoders 132 and 134, respectively, may determine on which of themultiple device levels of device 100 that the memory cells 110 to beaccessed are located.

A sense amplifier circuit 140 may operate to determine the value ofinformation read from memory cells 110 and provide the information inthe form of signals to lines 123 or lines 124. Sense amplifier circuit140 may also use the signals on lines 123 or lines 124 to determine thevalue of information to be written to memory cells 110. Memory device100 may include circuitry 150 to transfer information between memoryarray 102 and lines (e.g., data lines) 126. Signals DQ0 through DQN onlines 126 may represent information read from or written into memorycells 110. Lines 126 may include nodes within memory device 100 or pins(or solder balls) on a package where memory device 100 may reside. Otherdevices external to memory device 100 (e.g., a memory controller or aprocessor) may communicate with memory device 100 through lines 125,126, and 127.

Memory device 100 may perform memory operations such as a read operationto read information from memory cells 110 and a write operation(sometime referred to as a programming operation) to write (e.g.,program) information into memory cells 110. A memory control unit 118may control the memory operations based on control signals on lines 127.Examples of the control signals on lines 127 may include one or moreclock signals and other signals to indicate which operation, (e.g., awrite or read operation) that memory device 100 may perform. Otherdevices external to memory device 100 (e.g., a processor or a memorycontroller) may control the values of the control signals on lines 127.Specific values of a combination of the signals on the lines may producea command (e.g., a write or read command) that may cause memory device100 to perform a corresponding memory operation (e.g., a write or readoperation).

Each of memory cells 110 may be written to store informationrepresenting a value of a single bit (binary bit) or a value of multiplebits such as two, three, four, or other numbers of bits. For example,each of memory cells 110 may be written to store informationrepresenting a binary value “0” or “1” of a single bit. In anotherexample, each of memory cells 110 may be written to store informationrepresenting a value of multiple bits, such as one of four possiblevalues “00”, “01”, “10”, and “11” of two bits, one of eight possiblevalues “000”, “001”, “010”, “011”, “100”, “101”, “110” and “111”, or oneof other values of other number of multiple bits.

Memory device 100 may receive a supply voltage, including supply voltagesignals Vcc and Vss, on lines 141 and 142, respectively. Supply voltagesignal Vss may operate at a ground potential (e.g., having a value ofapproximately zero volts). Supply voltage signal Vcc may include anexternal voltage supplied to memory device 100 from an external powersource such as a battery or an alternating-current to direct-current(AC-DC) converter circuitry.

Circuitry 150 of memory device 100 may include a select circuit 152 andan input/output (I/O) circuit 116. Select circuit 152 may respond tosignals SEL0 through SELn to select the signals on lines 124 and 128that may represent the information read from or written into memorycells 110. Column decoder 134 may selectively activate the SEL0 throughSELn signals based on the A0 through AX address signals on lines 125.Select circuit 152 may select the signals on lines 124 and 128 toprovide communication between memory array 102 and I/O circuit 116during read and write operations.

Memory device 100 may include a non-volatile memory device and memorycells 110 may include non-volatile memory cells such that memory cells110 may retain information stored thereon when power (e.g., Vcc or Vss,or both) is disconnected from memory device 100. For example, memorydevice 100 may include a phase change memory device such that each ofmemory cells 110 may include a memory element having a material in whichat least a portion (e.g., programmable portion) of the material may bewritten to cause the portion to change between different phases, such asbetween a crystalline phase (or crystalline state) and an amorphousphase (or amorphous state). In each of memory cells 110, differentphases of the material of the programmable portion may cause the memorycell to have a different resistance state to represent different valueof the information stored therein.

Device 100 may selectively read or write memory cells 110. To write aselected memory cell 110, memory device 100 may apply a write currentthrough the selected memory cell to cause the memory element of theselected memory cell to change to a resistance state based on the valueof information to be stored therein. To read a selected memory cell 110,memory device 100 may apply a read current through the selected memorycell and then measure its resistance based on a read voltage todetermine the corresponding value of information stored therein.

One skilled in the art may recognize that memory device 100 may includeother features that are not shown in FIG. 1, to help focus on theembodiments described herein.

Memory device 100 may include at least one of the memory devices andmemory cells described below with reference to FIG. 2 through FIG. 24.

FIG. 2 shows a partial block diagram of a memory device 200 having amemory array 202 including memory cells 211, 212, 213, 214, 215, 216,217, 218, and 219 according to an embodiment of the invention. Memoryarray 202 may correspond to memory array 102 of FIG. 1. In FIG. 2,memory cells 211 through 219 may couple to lines 230, 231, and 232having signals Vx1, Vx2, Vx3, respectively, and lines 240, 241, and 242having signals Vy1, Vy2, and Vy3, respectively. Each of memory cells 211through 219 may include a memory element 222 and an access component 244coupled in series between one of lines 230, 231, and 232 and one oflines 240, 241, and 242. Each memory element 222 may include a materialthat may be written to various resistance states corresponding tovarious resistance values to represent different values of informationstored therein. During a read or write operation, memory device 200 mayuse appropriate voltage values for signals Vx1, Vx2, Vx3, Vy1, Vy2, andVy3 to turn on access component 244 of the memory cell that is beingselected (selected memory cell) to be read or written to access (e.g.,to read or write) the selected memory cell. Memory device 200 may turnoff access component 244 of each of the memory cells that is not beingselected (unselected memory cell).

For example, in a write operation, memory device 200 may select memorycell 215 to write information into it. In this example, memory device200 may turn on access component 244 of memory cell 215 and then apply awrite current through memory element 222 to cause its material to changefrom one resistance state to another resistance state. Thus, theresistance of a material of memory element 222 may also change from oneresistance value to another resistance value representing the value ofinformation to be stored in memory cell 215.

In another example, in a read operation, memory device 200 may selectmemory cell 215 to read information stored therein. In this example,memory device 200 may turn on access component 244 of memory cell 215and then apply a read current through memory element 222 and measure itsresistance (e.g., resistance of memory cell 215 between lines 231 and241) based on a read voltage to determine the corresponding value ofinformation stored therein. The read current may have a lower value thanthat of the write current so that the material of memory element 222 mayremain at the same resistance state to keep the information storedtherein at the same value after it is read. In both the write and readexamples herein, memory device 200 may turn off access component 244 ofeach of the unselected memory cells (memory cells 210, 211, 212, 213,216, 217, 218, and 219) so that memory element 222 of each of theunselected memory cells may remain unaccessed.

In the examples above, since memory cell 215 is assumed to be theselected memory cell, memory device 200 may use appropriate voltagevalues for signals Vx2 and Vy2 on lines 231 and 241 coupled to memorycell 215 so that a voltage difference (e.g., voltage drop) across memorycell 215 may have a sufficient value to turn on access component 244 ofmemory cell 215. When turned on, access component 244 of memory cell 215may allow conduction of current (e.g., read or write current) throughmemory element 222 of memory cell 215 so that memory device 200 may readinformation from or write information into memory cell 215. For theunselected memory cells, memory device 200 may use appropriate voltagevalues for signals Vx1, Vx3, Vy1, and Vy3 to keep off (or turn off)access component 244 of each of the unselected memory cells to preventconduction of current through the unselected memory cells.

Memory cells 211 through 219 may include a memory cell similar to oridentical to the memory cell of FIG. 3.

FIG. 3 shows a cross-section of a memory cell 310 with ionic conductionpath 399 according to an embodiment of the invention. Memory cell 310may include electrodes 301, 302, and 303, a memory element 333, and anaccess component 344. Signals Vx on line 323 of FIG. 3 may correspond toone of signals Vx1, Vx2, and Vx3 of FIG. 2. Signals Vy on line 324 ofFIG. 3 may correspond to one of signals Vy1, Vy2, and Vy3 of FIG. 2.

For clarity, the drawings described herein may omit some cross-sectionlines of some features. For example, FIG. 3 omits cross-section lines ofa part of access component 344.

In FIG. 3, the value of information stored in memory cell 310 may dependon the phase of the material of memory element 333. Memory element 333may include a material (e.g., phase change material) with a meltingpoint temperature Tm and a crystallization (or glass transition)temperature Tc. The resistance state of memory cell 310 may depend onthe phase (e.g., crystalline or amorphous phase) of the material ofmemory element 333. A current (e.g., write current) applied to memoryelement 333 may cause at least a portion of its material to changebetween different phases such as between crystalline and amorphousphases.

For example, during a write operation, a memory device (where memorycell 310 may reside) may apply a current (e.g., write current) to memorycell 310 to heat at least a portion of the material of memory element333 to a temperature above its melting point temperature Tm. The memorydevice may then allow the material of memory element 333 to coolrapidly, resulting in at least a portion (the melted portion) of thematerial to be in an amorphous phase corresponding to a resistance statewith a resistance value that may represent a value of the informationstored in memory cell 310. A different value of the current used duringthe write operation may result in a different resistance value. Thus,depending on the value of the information to be stored in memory cell310, the memory device may use one of various values for the currentduring a write operation to cause memory cell 310 to have an appropriateresistance value to reflect the value of the information to be storedtherein. To change the memory element from an amorphous phase to acrystalline phase, the memory device may apply a current to heat atleast a portion of the material of memory element 333 to a temperatureabove its crystallization temperature Tc but below its melting pointtemperature Tm. The memory device may then hold the material at sometemperature for a time sufficient to allow the material to crystallize(e.g., allow the amorphized portion to recrystallize). After thecrystallization, the material may have a crystallized phasecorresponding to a resistance state with a resistance value that mayrepresent a value of the information stored in memory cell 310. Thememory device may apply a current (e.g., read current) to read theinformation stored in memory cell 310 in ways similar to or identical toa read operation described above with reference to FIG. 2.

In FIG. 3, access component 344 may allow access to memory element 333during a read or write operation. Access component 344 may have anon-state and an off-state. FIG. 3 shows an example where accesscomponent 344 has an on-state. In the on-state, access component 344 mayinclude one or more conduction paths, such as a conduction path 399(continuous conduction path) formed between electrodes 302 and 303, toallow conduction of current through memory element 333 and between lines323 and 324. In the off-state, conduction path 399 may break or becomediscontinuous (not shown in FIG. 3) and prevent conduction of currentthrough memory element 333 and between lines 323 and 324. Thus, accesscomponent 344 has a higher resistance in the off-state to preventconduction of current and a lower resistance in the on-state to allowconduction of current.

Access component 344 may switch between the off-state (e.g., higherresistance) and the on-state (e.g., lower resistance) based on thevoltage values of signals Vx and Vy. For example, a difference involtage values (e.g., voltage potentials) between signals Vx and Vy maybe set to a positive value with respect to line 323 to switch accesscomponent 344 to the on-state when memory cell 310 is selected to beread or written. The difference in voltage values between signals Vx andVy may be set to a negative value with respect to line 323 when memorycell 310 is not selected to be read or written.

Access component 344 may include a material that excludes silicon(non-silicon based material), e.g., ion conducting chalcogenidematerial, binary metal oxide material, perovskite oxide material. In theon-state, ions (e.g., positively charged ions) of one of the materialsof access component 344, such as ions 388, may migrate into othermaterials to form an ionic conduction path 399. As shown in FIG. 3,conduction path 399 may include ions 388 forming a continuous pathbetween electrodes 302 and 303 to conduct current when access component344 is in the on-state. In the off-state, the continuity of conductionpath 399 may be broken (e.g., conduction path 399 includes adiscontinuous segment), thereby preventing conduction of current betweenelectrodes 302 and 303.

In memory cell 310, electrodes 301, 302, and 303 may serve as contactsand help pass current through memory element 333 and access component344. Examples of the material of electrodes 301, 302, and 303 mayinclude refractory metal nitride, carbides and borides such as TiN, ZrN,HfN, VN, NbN, TaN, TiC, ZrC, HfC, VC, NbC, TaC, TiB2, ZrB2, HfB2, VB2,NbB2, TaB2, Cr3C2, Mo2C, WC, CrB2, Mo2B5, W2B5; compounds such as TiAlN,TiSiN, TiW, TaSiN, TiCN, SiC, B4C, WSix, MoSi2; metal alloys such asNiCr; and elemental materials such as doped silicon, carbon, platinum,niobium, tungsten, molybdenum.

As described above, memory element 333 may include a phase changematerial. Some phase change materials may include chalcogenide materialswith various combinations of germanium (Ge), antimony (Sb), tellurium(Te), and other similar materials. Examples of phase change materialsmay include binary combinations such as germanium telluride (GeTe),indium selenide (InSe), antimony telluride (SbTe), gallium antimonide(GaSb), indium antimonide (InSb), arsenic telluride (AsTe), aluminumtelluride (AlTe); ternary combinations such as germanium antimonytelluride (GeSbTe, e.g., Ge₂Sb₅Te₅), tellurium germanium arsenide(TeGeAs), indium antimony telluride (InSbTe), tellurium tin selenide(TeSnSe), germanium selenium gallide (GeSeGa), bismuth seleniumantimonide (BiSeSb), gallium selenium telluride (GaSeTe), tin antimonytelluride (SnSbTe), indium antimony germanide (InSbGe); and quaternarycombinations such as tellurium germanium antimony sulfide (TeGeSbS),tellurium germanium tin oxide (TeGeSnO), and alloys of telluriumgermanium tin gold, palladium tellurium germanium tin, indium seleniumtitanium cobalt, germanium antimony tellurium palladium, germaniumantimony tellurium cobalt, antimony tellurium bismuth selenium, silverindium antimony tellurium, germanium antimony selenium tellurium,germanium tin antimony tellurium, germanium tellurium tin nickel,germanium tellurium tin palladium, and germanium tellurium tin platinum,and others. Among the phase change materials listed herein, some mayprovide an appropriate choice over the others depending in part on theapplication of the device. For example, Ge₂Sb₅Te₅ (germanium antimonytelluride) may be an appropriate choice for a phase change memorydevice, in part, because of its relatively quick switching speed (e.g.,a few nanoseconds) between different resistance states. Most of thematerial compositions in this description list only the componentelements. The relative amount of each component element in each of thesematerial compositions is not limited to a particular value.

The above description uses phase change materials for memory element 333only as example materials. Memory element 333 and other memory elementsdescribed herein may include other unipolar switching memory materialsbesides phase change materials. Unipolar switching memory materialsinclude materials that can switch in resistance such that they can haveone resistance (e.g., resistance corresponding to one value ofinformation) when one voltage is applied to the material in onedirection and another resistance (e.g., resistance corresponding toanother value of information) when another voltage with the samepolarity is applied to the material in the same direction.

As described above, access component 344 may include material excludingsilicon such as ion conducting chalcogenide material, binary metal oxidematerial, or perovskite oxide material. Access component 344 may alsoinclude other bipolar switching materials. Bipolar switching materialsinclude materials that can switch in resistance such that they can turnon to have an on-resistance state (e.g., state to allow conduction ofcurrent) when a voltage with a polarity is applied to the material inone direction and turn off to have an off-resistance state (e.g., stateto prevent conduction of current) when another voltage with the oppositepolarity is applied to the material in the same direction. Theon-resistance state may stay when the voltage is being applied ordisappear when the voltage is removed. Thus, the bipolar switchingmaterials used herein may or may not include switching memory materials.

The perovskite oxide material of access component 344 may include one ofstrontium titanium oxide (SrTiO), strontium zirconium oxide (SrZrO), andbarium titanium oxide (BaTiO).

The binary metal oxide material of access component 344 may include oneof hafnium oxide (HfO), nobium oxide (NbO), aluminum oxide (AlO),tunstung oxide (WO), titanium oxide (TaO), titanium oxide (TiO),zirconium oxide (ZrO), copper oxide (CuO), iron oxide (FeO), and nickeloxide (NiO).

The ion conducting chalcogenide material of access component 344 mayinclude a chalcogenide based material doped with a material (e.g.,metal). The ion conducting chalcogenide material may use ions (e.g.,positively charged ions) to form one or more conduction paths (such asconduction path 399 of FIG. 3) to change the resistance of accesscomponent 344 between different resistance values when appropriatevalues (e.g., voltage values) of the signals are applied across accesscomponent 344. For example, the ion conducting chalcogenide material maybe a silver-doped or copper-doped chalcogenide material, such assilver-doped germanium selenide, copper-doped germanium selenide,silver-doped germanium sulfide, or copper-doped germanium sulfide. Eachof these silver-doped and copper-doped chalcogenide materials mayinclude multiple layers. For example, access component 344 may includemultiple layers of materials between electrodes 302 and 303 in which themultiple layers may include silver-doped germanium selenide having alayer of germanium selenide (GeSe), a layer of copper selenide (CuSe),silver selenide (AgSe) or tin selenide (SnSe), a layer of germaniumselenide (GeSe), a layer of silver (Ag), and a layer of germaniumselenide (GeSe). In another example, access component 344 may includemultiple layers in which the multiple layers may include silver-dopedgermanium sulfide having a layer of germanium sulfide (GeS), a layer ofsilver selenide (AgSe) or tin selenide (SnSe) or copper selenide (CuSe),a layer of germanium sulfide (GeS), a layer of silver (Ag), and a layerof germanium sulfide (GeS).

The example materials of access component 344 and the materials ofmemory element 333, such as those listed above, may have similar processtemperature tolerances. Therefore, processes of making a memory cellsuch as memory cell 310 may be improved in comparison to those of makinga conventional memory cell where the material of the access componentand the material of the memory element may have different processtemperature tolerances.

FIG. 4 is an example embodiment illustrating a graph of I-Vcharacteristics showing on-state and off-state of access component 344of memory cell 310 of FIG. 3. FIG. 4 shows two voltage values: voltagevalue Vt_(ON) greater than zero, and voltage Vt_(OFF) less than zero.Voltage values Vt_(ON) and Vt_(OFF) may correspond to threshold voltagevalues of access component 344. Access component 344 may turn on or offbased on the relationship among voltage values shown in expression (1)and (2) below.Access component 344 may turn on when Vx−Vy>Vt _(ON)>0.  (1)Access component 344 may turn off when Vx−Vy<Vt _(OFF)<0.  (2)

Expression (2) may be rewritten as expression (3):Vy−Vx>Vt′ _(OFF)>0 (where Vt′ _(OFF) =−Vt _(OFF).)  (3)

In expression (1), the difference between Vx and Vy (Vx minus Vy) may beconsidered as a voltage difference (Vx−Vy) in a first direction (e.g.,direction from line 323 to line 324 in FIG. 3) across memory element 333and access component 344. Thus, based on expression (1), accesscomponent 344 may turn on when a voltage difference (Vx−Vy) in a firstdirection across memory element 333 and access component 344 exceedsvoltage value Vt_(ON) and is greater than zero volts. As described abovewith reference to FIG. 3, access component 344, when turned on, mayallow conduction of current through memory element 333 or accesscomponent 344 (or both).

In expression (2), the difference between Vx and Vy is less thanVt_(OFF) and less than zero volts. Thus, the difference (Vx−Vy) is anegative value in the first direction. However, instead of describingexpression (2) in terms of the negative value in a first direction, thedescription herein may alternatively use expression (3) to describe anequivalent of expression (2) in terms of a positive value in an oppositedirection (e.g., second direction).

In expression (3), the difference between Vy and Vx (Vy minus Vx) may beconsidered as a voltage difference (Vy−Vx) in a second direction (e.g.,direction from line 324 to line 323 in FIG. 3) across memory element 333and access component 344. Thus, based on expression (3), accesscomponent 344 may turn off when a voltage difference (Vy−Vx) in a seconddirection across memory element 333 and access component 344 exceedsvoltage value Vt′_(OFF) and is greater than zero volts. As describedabove with reference to FIG. 3, access component 344, when turned off,may prevent conduction of current through memory element 333 or accesscomponent 344 (or both). In other words, as shown in expression (2),access component 344 may turn off when Vx−Vy is a negative value lessthan Vt_(OFF).

Depending on the material of access component 344, voltage value Vt_(ON)may have an absolute value that is about 2 to 2.5 times greater than theabsolute value of voltage value Vt_(OFF). For example, when accesscomponent 344 has a material such as the material of access component544 of FIG. 5, voltage value Vt_(ON) may have a value of about 0.25 voltand voltage value Vt_(OFF) may have a value of about negative 0.1 (−0.1)volt.

FIG. 4 also shows regions 411, 412, and 413, and curves 421 and 422.Region 411 may include voltage values from Vt_(ON) and greater. Region413 may include voltage values from Vt_(OFF) and lower. Region 412 mayinclude a voltage value between Vt_(ON) and Vt_(OFF). Access component344 may be configured to operate in the on-state corresponding to region411 (e.g., Vx−Vy>Vt_(ON)>0) and in the off-state corresponding to region413 (e.g., Vx−Vy<Vt_(OFF)<0). Region 412 may be called a hysteresisswitching region of access component 344 where access component 344 maybe in either the on-state or the off-state.

Curve 421 in FIG. 4 may show the relationship between voltage andcurrent of access component 344 when access component 344 switches froman off-state to an on-state. For example, when access component 344 isin an off-state (e.g., conduction path 399 in FIG. 3 may be broken) andwhen line 324 is coupled to a ground potential (e.g., Vy=0), accesscomponent 344 may turn on and switch from the off-state (region 413 inFIG. 4) to the on-state (region 411) to allow conduction of current(indicated by current flow direction 431) when the voltage value of line323 (e.g., Vx) is greater than Vt_(ON) (Vx>Vt_(ON)).

Curve 422 in FIG. 4 may show the relationship between voltage andcurrent of access component 344 when access component 344 switches froman on-state to an off-state. For example, when access component 344 isin an on-state (e.g., conduction path 399 in FIG. 3 is continuous) andwhen line 323 is coupled to a ground potential (e.g., Vx=0), accesscomponent 344 may turn off and switch from the on-state (region 411 inFIG. 4) to the off-state (region 413) to prevent conduction of currentwhen the voltage value of line 324 (e.g., Vy) is greater than Vt′_(OFF)(Vy>Vt′_(OFF)). As shown by the portion of curve 422 in region 412, someamount of current (indicated by current flow direction 432) may followthrough access component 344 when access component 344 is in region 412(hysteresis switching region) during switching from region 411(on-state) to region 413 (off-state). However, when the voltage value ofVy is greater than Vt′_(OFF), access component 344 may leave region 412and switch to region 413 and prevent conduction of current. As shown byportion of curve 422 in region 413 (off-state), the value of current maybe substantially small or equal to zero.

Besides the characteristics such as the material and the functionsdescribed above with reference to FIG. 3 and FIG. 4, access component344 may include at least the following characteristics. Access component344 may switch between the off-state and the on-state in a relativelyshorter time (e.g., in about one nanosecond for material such assilver-doped chalcogenide) than that of memory element 333. Accesscomponent 344 may be turned off by a relatively smaller amount ofcurrent than a write current to write memory element 333, and may have arelatively large ratio of on current (Ion) to off current (Ioff), e.g.,Ion/Ioff ratio of few hundred micro-amperes/pico-amperes range. Accesscomponent 344 may have a resistance of a few kilo-ohms when it is in theon-state, and a resistance of about more than one mega-ohms when it isin an off-state. The characteristics of access component 344, asdescribed above, may enable it to be useful as access component to allowor prevent conduction of current to and from memory element 333.

In memory cell 310 of FIG. 3, access component 344 and memory element333 may include materials having similar process temperature tolerance.Therefore, memory cell 310, having access component 344 and memoryelement 333 as described above, may provide a suitable option to form amemory device with multiple device levels where memory cells may bestacked in the multiple device levels to increase storage density. Insome conventional memory devices, the access component (comparing toaccess component 344) and the memory element (comparing to memoryelement 333) of the memory cell may include different processtemperature tolerances; therefore, forming multiple device levels ofmemory cells in a conventional device may pose challenges. For example,in a conventional device, the memory element may have a lower processtemperature tolerance than that of the access component (e.g.,silicon-based access component). Therefore, thermal damage to the memoryelement in the lower device level may occur when the access component ina higher device level is formed. In contrast, as described above, sinceaccess component 344 and memory element 333 of FIG. 3 may includematerials having similar process temperature tolerances, thermal damagemay be avoided when multiple device levels of memory cells are formed.

FIG. 5 shows cross-section of a memory cell 510 including an accesscomponent 544 having ion conducting chalcogenide material according tovarious embodiments of the invention. Memory cell 510 may also includeelectrodes 501, 502, and 503, and a memory element 555 coupled in serieswith access component 544 between electrodes 501 and 503. As shown inFIG. 5, access component 544 may include an example of multiple layers561, 562, 563, 564, and 565 with example materials such as germaniumselenide (e.g., Ge₄Se₆) for layer 561, silver selenide (Ag₂Se) or tinselenide (SnSe) for layer 562, germanium selenide (e.g., Ge₄Se₆) forlayer 563, silver (Ag) for layer 564, and germanium selenide (e.g.,Ge₄Se₆) for layer 565. The materials of access component 544 shown inFIG. 5 may be considered an example of a silver-doped chalcogenidematerial. FIG. 5 shows the ion conducting chalcogenide material foraccess component 544 being silver-doped chalcogenide as an example.Access component 544, however, may include another chalcogenide materialdoped with another material (besides silver).

Layers 561, 562, 563, 564, and 565 of access component 544 may havethicknesses of about 15 nm (nanometers), about 47 nm, about 15 nm, about20 nm, and about 10 nm, respectively. The term “about” with respect to aspecific thickness value means that the thickness may be less than orgreater than the specific thickness value by a margin. The margin mayhave a value equal from one percent (%) to 20% of the specific value.Access component 544 may include other thickness values for layers 561,562, 563, 564, and 565. However, the specific example thickness valuesdescribed herein may improve at least one of a switching time betweenon-state and off-state and a reduction in resistance of access component544 in the on-state. Access component 544 may include fewer or morelayers than those shown in FIG. 5, with materials similar to oridentical to those of the materials of access component 344 of FIG. 3.Electrodes 501, 502, and 503 may include materials similar to oridentical to those of electrodes 301, 302, and 303 of FIG. 3.

Access component 544 may include I-V characteristics similar to oridentical to that of access component 344 of FIG. 4. For example, accesscomponent 544 may have an on-state when electrodes 501 and 503 haveappropriate voltage values (e.g., voltage values that may satisfyexpression (1) above) and an off-state when electrodes 501 and 503 haveother appropriate voltage values (e.g., voltage values that may satisfyexpression (2) above). In the on-state, silver ions (Ag⁺) from thesilver-doped chalcogenide material of access component 544 may form aconduction path between electrodes 502 and 503 to allow conduction ofcurrent through access component 544 and memory element 555. In theoff-state, the conduction path formed by the silver ions may break andprevent conduction of current through access component 544 and memoryelement 555.

FIG. 6 shows a cross-section of a memory cell 610 including an accesscomponent 644 having binary metal oxide material according to anembodiment of the invention. Memory cell 610 may also include electrodes601, 602, and 603, and a memory element 666 coupled in series withaccess component 644. Access component 644 may include materials similarto or identical to those of the binary metal oxide materials of accesscomponent 344 of FIG. 3. Access component 644 may include I-Vcharacteristics similar to or identical to that of access component 344of FIG. 4. For example, access component 644 may have an on-state whenelectrodes 601 and 603 have appropriate voltage values (e.g., voltagevalues that may satisfy expression (1) above) and an off-state whenelectrodes 601 and 603 have other appropriate voltage values (e.g.,voltage values that may satisfy expression (2) above). In the on-state,ions or vacancies from the binary metal oxide material of accesscomponent 644 may form a conduction path between electrodes 602 and 603to allow conduction of current through access component 644 and memoryelement 666. Examples of ions include copper ions Cu⁺ if the binarymetal oxide material is copper oxide, and iron ions Fe²⁺ if the binarymetal oxide material is iron oxide. An example of vacancies includesoxygen vacancies O²⁻ if the binary metal oxide material is nickel oxide.In the off-state, the conduction path formed by the ions of the binarymetal oxide (e.g., ions Cu⁺ or Fe²⁺, or O²⁻ vacancies) may break andprevent conduction of current through access component 644 and memoryelement 666.

FIG. 7 shows a cross-section of a memory cell 710 including an accesscomponent having perovskite oxide material according to an embodiment ofthe invention. Memory cell 710 may also include electrodes 701, 702, and703, and a memory element 777 coupled in series with access component744. Access component 744 may include materials similar to or identicalto those of the perovskite oxide materials of access component 344 ofFIG. 3.

FIG. 8 shows a partial schematic diagram of a memory device 800 having amemory array 802 according to an embodiment of the invention. Memoryarray 802 may include memory cells 811 through 819 and 821 through 829.These memory cells are collectively called “the” memory cells in FIG. 8.As shown in FIG. 8, each of the memory cells may include a memoryelement 888 and an access component 844, which may be similar to oridentical to the memory element and the access component of memory cell310, 510, 610, or 710 described above with reference to FIG. 3 throughFIG. 7. In FIG. 8, memory device 800 may select the memory cells usingsignals Vx1, Vx2, Vx3, Vx4, Vx5, and Vx6 on lines 831, 832, 833, 834,835, and 836, respectively, and signals Vy1, Vy2, and Vy3 on lines 841,842, and 843, respectively. During a read or write operation, memorydevice 800 may use appropriate voltage values of signals Vx1 through Vx6and Vy1 through Vy3 to turn on the access component of a selected memorycell that is to be read or written and turn off the access components ofthe unselected memory cells.

Access component 844 of each of the memory cells in FIG. 8 may includetwo threshold voltages having voltage values such as voltage valuesVt_(ON) and Vt_(OFF) similar to or identical those of access component344 described above with reference to FIG. 4. In FIG. 8, accesscomponent 844 of the selected memory cell may turn on when the voltagedifference across the selected memory cell with respect to a firstdirection (e.g., direction from access component 844 to memory element888) is greater than Vt_(ON). Access component 844 of each of theunselected memory cells may turn off when the voltage difference acrosseach of the unselected selected memory cells with respect to a seconddirection (e.g., direction from memory element 888 to access component844) is greater than Vt′_(OFF) (or is less than Vt_(OFF) if the voltagedifference is considered with respect to the first direction).

The following example assumes that access component 844 of each of thememory cells is in an off-state, and that memory device 800 selects toaccess memory cell 815 to either read or write memory cell 815. In thisexample, memory device 800 may selectively use voltage values +V and 0(as shown in FIG. 8) for signals Vx1 through Vx6 and Vy1 through Vy3, sothat memory device 800 may turn on access component 844 of memory cell815 (and then apply a read or write current through memory element 888)and keep access component 844 of each of the other memory cells in theoff-state.

Voltage value +V in FIG. 8 may have a value greater than voltage valueVt_(ON) and Vt′_(OFF). Thus, in this example, the voltage differenceacross memory cell 815 is equal to the voltage (+V) on line 834 minusthe voltage (zero) on line 842. Since voltage value +V is greater thanVt_(ON), the voltage difference across memory cell 815 is greater thanVt_(ON). Therefore, using the example voltage values of FIG. 8, memorydevice 800 may turn on access component 844 of selected memory cell 815.The voltage difference across unselected memory cell 825 is equal to thevoltage (zero) on line 842 minus the voltage (+V) on line 833. Thus, thevoltage difference across memory cell 825 is −V, which is less thanVt_(OFF). Therefore, access component 844 of selected memory cell 825may remain in the off-state.

The voltage values +V and zero are used in the example above only forease of describing the example. Memory device 800 may use values besideszero volts such that the voltage difference across in the direction fromaccess component 844 to memory element is greater than voltage valueVt_(ON) for the selected memory cell and is less than Vt_(OFF) for theunselected memory cell.

Memory device 800 may include multiple device levels such that a firstgroup of the memory cells may be located on one device level and asecond group of the memory cells may be located on another device leveland stacked on the first group.

FIG. 9 through FIG. 11 show 3-D views of some memory devices with asingle device level and multiple device levels.

FIG. 9 shows a partial 3-D view of a memory device 900 having memorycells 910 located on a single device level 991 according to anembodiment of the invention. FIG. 9 also shows x-y-z dimensions for easeof describing relative positions of the features of memory device 900.For example, as shown in FIG. 9, memory cells 910 may be arranged inrows and columns along the x-dimension and y-dimension, respectively,and may be located on device level 991 of the z-dimension.

Each memory cell 910 may include electrodes 901, 902, 903, and an accesscomponent 944 coupled in series with memory element 999 between line 930or 931 and line 940 or 941. As shown in FIG. 9, electrodes 901, 902, and903, access component 944, and memory element 999 of each memory cell910 may have a cylindrical structure extending in the z-direction suchthat a cross-section of memory cell 910 (e.g., a cross-section of memoryelement 999, or access component 944, or each of electrodes 901, 902,and 903) parallel to the x-y plane may have a circular or substantiallycircular shape. The circular or substantially circular shape hereinincludes an elliptical or substantially elliptical shape. Memory element999 may have other shapes.

Lines 930, 931, 940 and 941 of FIG. 9 may correspond to lines 230, 231,240 and 241 respectively, of FIG. 2. In FIG. 9, lines 930, 931, 940, and941 may include conductive material, such as metal (e.g., copper,aluminum, gold, or others), and may be called metal lines of memorydevice 900. Memory element 999 may include material similar to oridentical to those of memory element 333 of FIG. 3, e.g., phase changematerial (such as chalcogenide) or other unipolar switching memorymaterials. Access component 944 may include materials similar to oridentical to those of access component 344 of FIG. 4, e.g., ionconducting chalcogenide, binary metal oxide, or perovskite oxide, orother bipolar switching materials.

FIG. 10 shows a partial 3-D view of a memory device 1000 having memorycells 1010 stacked on multiple device levels 1091 and 1092 according toan embodiment of the invention. As shown in FIG. 10, device level 1092may be stacked over device level 1091 in the z-dimension in which eachof device levels 1091 and 1092 may includes a number of memory cells1010 arranged in rows and columns along the x-dimension and y-dimension,respectively. Each memory cell 1010 may include electrodes 1001, 1002,and 1003, and an access component 1044 coupled in series with memoryelement 1011 between its respective lines (e.g., conductive lines suchas metal lines) 1030, 1031, 1032, 1033, and 1040, 1041, 1042, and 1043.The materials of the features of memory device 1000, e.g., accesscomponent 1044 and memory element 1011, may be similar to or identicalto those of memory device 900 of FIG. 9. Lines 1030, 1031, 1040, and1041 of FIG. 10 may correspond to lines 230, 231, 240 and 241respectively, of FIG. 2. Lines 1032, 1033, 1042, and 1043 of FIG. 10 maycorrespond to lines 230, 231, 240 and 241 respectively, of FIG. 2.

FIG. 11 shows a partial 3-D view of a memory device 1100 having memorycells stacked on multiple device levels with shared conduction linesbetween device levels according to an embodiment of the invention. Asshown in FIG. 11, device level 1192 may be stacked over device level1191 in the z-dimension in which each of device levels 1191 and 1192 mayinclude a number of memory cells 1110 arranged in rows and columns alongthe x-dimension and y-dimension, respectively. Each memory cell 1110 mayinclude electrodes 1101, 1102, 1103, and an access component 1144coupled in series with memory element 1111 between its respective lines(e.g., conductive lines such as metal lines) 1131, 1133, 1132, or 1134,and 1141 or 1142. Lines 1131, 1133, 1132, and 1134 of FIG. 11 maycorrespond to lines 831, 833, 832, and 834, respectively, of FIG. 8.Lines 1141 and 1142 of FIG. 11 may correspond to lines 841 and 842,respectively, of FIG. 8. In FIG. 11, the materials of the features ofmemory device 1100, e.g., access component 1144 and memory element 1111,may be similar to or identical to those of memory device 900 of FIG. 9.As shown in FIG. 1, two memory cells 1110 from different device levelsmay share the same line, such as lines 1141 or 1142. Sharing the sameline 1141 or 1142 may reduce device size and simplify fabricationprocess.

FIG. 12 through FIG. 17 show various processes of forming a memorydevice 1200 according to an embodiment of the invention. Memory device1200 (shown in more details in FIG. 17) may correspond to memory device900 of FIG. 9. In FIG. 12 through FIG. 17, the cross-section view of thefeatures of memory device 1200 may correspond to a cross-section view ofsimilar features shown in memory device 900, looking in the y-dimension(or into the paper) of FIG. 9. For clarity, FIG. 12 through FIG. 17include cross-section lines for only some of the features therein.

As shown in FIG. 12, a conductive line 1230 has been formed over asubstrate 1212. As used herein, the term “on” used with respect to twoor more materials, one “on” the other, means at least some contactbetween the materials, while “over” means the materials are in closeproximity, but possibly with one or more additional interveningmaterials such that contact is possible but not required. Neither “on”nor “over” implies any directionality as used herein unless stated assuch. In FIG. 12, substrate 1212 may include material such astetraethoxysilane (TEOS), or silicon nitride, or other insulationmaterial. Forming conductive line 1230 may include depositing a layer ofmaterial over substrate 1212 and patterning the layer to form conductiveline 1230. Alternatively, forming conductive line 1230 may include adamascene process. The material of conductive line 1230 may be similarto or identical to those of line 930 of FIG. 9. Conductive line 1230 mayhave a greater dimension (e.g., length) extending along the x-dimensionsimilar to the x-dimension of FIG. 9.

In FIG. 13, an insulator 1313 and electrodes 1301 have been formed.Forming insulator 1313 may include depositing an insulation materialover substrate 1212 followed by a polishing process such as chemicalmechanical polishing (CMP) planarization. Forming electrodes 1301 mayinclude removing some portions of insulator 1313 and depositing materialin the removed portion of insulator 1313. The material of electrodes1301 may be similar to or identical to electrode 301 of FIG. 3.

In FIG. 14 multiple layers 1444, 1402, 1461, 1462, 1463, 1464, 1465, and1403 have been formed. Forming these multiple layers may includedepositing layer 1444 directly contacting electrodes 1301, anddepositing the other layers 1402, 1461, 1462, 1463, 1464, 1465, and 1403over layer 1444. Layer 1444 may include materials similar to oridentical to those of memory element 333 of FIG. 3; layers 1402 and 1403may include materials similar to or identical to those of electrodes 302and 303, respectively, of FIG. 3; and layers 1461, 1462, 1463, 1464, and1465 may include materials similar to or identical to those of layers561, 562, 563, 564, and 565, respectively, of access component 555 ofFIG. 5.

In FIG. 15, memory cells 1510 have been formed. Forming memory cells1510 may include patterning layers 1444, 1402, 1461, 1462, 1463, 1464,1465, and 1403 of FIG. 14 into mesas or pillars (as shown FIG. 15) thatmay form a part of memory cells 1510. Each of memory cells 1510 mayinclude electrodes 1301, 1502, and 1503, memory element 1555, and accesscomponent 1544 having multiple layers 1461, 1462, 1463, 1464, and 1465of FIG. 14 that have been patterned in FIG. 15. FIG. 14 shows fivelayers 1461, 1462, 1463, 1464, and 1465 as an example. Forming accesscomponent 1544 may alternatively include forming fewer or more than fivelayers so that access component 1544 (FIG. 15) may include materialsimilar to or identical to those of access component 344 of FIG. 3.

In FIG. 16, an insulator 1613 has been formed. Forming insulator 1613may include depositing an insulator material over the features of memorycells 1510 of FIG. 15 and then performing a polishing process, such asCMP. The polishing process may stop on electrodes 1503. Alternatively,an additional thin encapsulating layer (e.g., silicon nitride) may beformed before insulator 1613 is formed to protect memory cells 1510.

In FIG. 17, conductive lines 1740 and 1741 and an insulator 1713 havebeen formed. Forming conductive lines 1740 and 1741 may includedepositing a conductive material over insulator 1613 and electrodes1503, and patterning the conductive material to form conductive lines1740 and 1741 such that conductive lines 1740 and 1741 may beperpendicular (or substantially perpendicular) to conductive line 1230.Alternatively, forming conductive lines 1740 may include a damasceneprocess. Forming insulator 1713 may include depositing an insulationmaterial over insulator 1613 and conductive lines 1740 and 1741, andthen performing a polishing process, such as CMP. The polishing processmay stop on conductive lines 1740 and 1741. The material of conductivelines 1740 and 1741 may be similar to or identical to those of line 940and 941 of FIG. 9. In FIG. 17, each of conductive lines 1740 and 1741may have a greater dimension (e.g., length) extending along they-dimension similar to the y-dimension of FIG. 9.

FIG. 18 and FIG. 19 show various processes of forming a memory device1800 having multiple device levels according to an embodiment of theinvention. Memory device 1800 (shown in more details in FIG. 19) maycorrespond to memory device 1000 of FIG. 10. In FIG. 18 and FIG. 19, thecross-section view of the features of memory device 1800 may correspondto a cross-section view of similar features shown in memory device 1000,looking in the y-dimension of FIG. 10. For clarity, FIG. 18 and FIG. 19include cross-section lines for only some of the features therein.

In FIG. 18, device level 1891 having memory cells 1810 has been formed.Forming device level 1891 may include processes similar to or identicalto those of the processes described above with reference to FIG. 12through FIG. 17. Thus, similar or identical features among FIG. 12through FIG. 17 and FIG. 18 and FIG. 19 have the same reference numbers.In FIG. 18, an insulator 1813 has been formed over device level 1891.Forming insulator 1813 may include depositing an insulation materialover device level 1891.

In FIG. 19, another device level 1992 having memory cells 1910 has beenformed over device level 1891. Forming device level 1992 may includeprocesses similar to or identical to those of the processes describedabove with reference to FIG. 12 through FIG. 17. In FIG. 19, devicelevel 1992 may be stacked over device level 1891 in the z-dimensionsimilar to the z-dimension of FIG. 10. In memory device 1800 of FIG. 19,each of memory cells 1810 and 1910 may include materials similar to oridentical to those of memory cell 310 of FIG. 3. Thus, the accesscomponents and memory elements of memory cells 1810 and 1910 may includematerials with similar process temperature tolerance. Therefore, damage(e.g., thermal damage) to memory cells 1810, such as thermal damage tomemory elements of memory cells 1810, may be avoided when memory cells1910 on device level 1992 are formed, resulting in formation of memorydevice 1800 with multiple stacked device levels.

FIG. 20 through FIG. 24 show various processes of forming a memorydevice 2000 having multiple device levels with shared conduction linesaccording to an embodiment of the invention. Memory device 2000 (shownin more details in FIG. 24) may correspond to memory device 1100 of FIG.11. In FIG. 20 through FIG. 24, the cross-section view of the featuresof memory device 2000 may correspond to a cross-section view of similarfeatures shown in memory device 1100, looking in the y-dimension of FIG.11. For clarity, FIG. 20 through FIG. 24 include cross-section lines foronly some of the features therein.

In FIG. 20, device level 2091 having memory cells 2010 has been formed.Forming device level 2091 may include processes similar to or identicalto those of the processes described above with reference to FIG. 12through FIG. 17. Thus, similar or identical features among FIG. 12through FIG. 17 and FIG. 20 through FIG. 24 have the same referencenumbers. In FIG. 20, an insulator 2013 and electrodes 2001 have beenformed over device level 2091. Forming insulator 2013 may includedepositing an insulation material over device level 2091. Formingelectrodes 2001 may include removing some portions of insulator 2013 anddepositing material in the removed portion of insulator 2013. Thematerial of electrodes 2013 may be similar to or identical to electrode301 of FIG. 3.

In FIG. 21 multiple layers 2111, 2102, 2161, 2162, 2163, 2164, 2165, and2103 have been formed. Layer 2111 may include material similar to oridentical to those of memory element 333 of FIG. 3; layers 2102 and 2103may include materials similar to or identical to those of electrodes 302and 303, respectively, of FIG. 3; and layers 2161, 2162, 2163, 2164, and2165 may include materials similar to or identical to those of layers561, 562, 563, 564, and 565, respectively, of access component 555 ofFIG. 5.

In FIG. 22, memory cells 2210 have been formed. Forming memory cells2210 may include patterning layers 2111, 2102, 2161, 2162, 2163, 2164,2165, and 2103 of FIG. 21 into mesas or pillars (as shown FIG. 22) thatmay form a part of memory cells 2210. Each of memory cells 2210 mayinclude electrodes 2001, 2202, and 2203, memory element 2222, and accesscomponent 2244 having multiple layers 2161, 2162, 2163, 2164, and 2165of FIG. 21 that have been patterned in FIG. 22. FIG. 21 shows fivelayers 2161, 2162, 2163, 2164, and 2165 as an example. Forming accesscomponent 2244 may alternatively include forming fewer or more than fivelayers so that access component 2244 (FIG. 22) may include materialsimilar to or identical to those of access component 344 of FIG. 3.

In FIG. 23, an insulator 2313 has been formed. Forming insulator 2313may include depositing an insulator material over the features of memorycells 1510 of FIG. 15 and then performing a polishing process, such asCMP. The polishing process may stop on electrodes 2203. Alternatively,an additional thin encapsulating layer (e.g., silicon nitride) may beformed before insulator 2313 is formed to protect memory cells 2210.

In FIG. 24, conductive line 2432 has been formed. Forming conductiveline 2432 may include depositing a conductive material over insulator2313 and electrodes 2203, and patterning the conductive material to formconductive line 2432 such that conductive line 2432 may be perpendicular(or substantially perpendicular) to conductive lines 1740 and 1741 andparallel (or substantially parallel) to conductive line 1230.Alternatively, forming conductive line 2432 may include a damasceneprocess. The material of conductive line 2432 may be similar to oridentical to those of lines 1132 and 1134 of FIG. 11. In FIG. 24,conductive line 2432 may have a greater dimension (e.g., length)extending along the x-dimension similar to the x-dimension of FIG. 11.

As shown in FIG. 24, memory device 2000 may include device level 2091and device level 2492, which may be stacked over device level 2091 inthe z-dimension similar to the z-dimension of FIG. 11. In memory device2000 of FIG. 24, each of memory cells 2010 and 2210 may includematerials similar to or identical to those of memory cell 310 of FIG. 3.Thus, the access components and memory elements of memory cells 2010 and2210 may include materials with similar process temperature tolerance.Therefore, damage (e.g., thermal damage) to memory cells 2010, such asthermal damage to memory elements of memory cells 2010, may be avoidedwhen memory cells 2210 on device level 2492 are formed, resulting information of memory device 2000 with multiple stacked device levels.

One or more embodiments described herein include apparatus and methodshaving a memory element configured to store information and an accesscomponent configured to allow conduction of current through the memoryelement when a first voltage difference in a first direction across thememory element and the access component exceeds a first voltage value,and to prevent conduction of current through the memory element when asecond voltage difference in a second direction across the memoryelement and the access component exceeds a second voltage value, whereinthe access component includes a material excluding silicon. Otherembodiments including additional apparatus methods are described abovewith reference to FIG. 1 through FIG. 24.

The illustrations of apparatus such as memory devices 100, 200, 800,900, 1000, 1100, 1200, 1800, and 2000, and memory cells 110, 211 though219, 811 through 819, 821 through 829, 910, 1010, 1110, 1510, 1810,1910, 2010, and 2210 are intended to provide a general understanding ofthe structure of various embodiments and not a complete description ofall the elements and features of the apparatus that might make use ofthe structures described herein.

The apparatus of various embodiments may include or be included inelectronic circuitry used in high-speed computers, communication andsignal processing circuitry, memory modules, portable memory storagedevices (e.g., thumb drives), single or multi-processor modules, singleor multiple embedded processors, multi-core processors, data switches,and application-specific modules including multilayer, multi-chipmodules. Such apparatus may further be included as sub-components withina variety of electronic systems, such as televisions, cellulartelephones, personal computers (e.g., laptop computers, desktopcomputers, handheld computers, tablet computers, etc.), workstations,radios, video players, audio players (e.g., MP3 (Motion Picture ExpertsGroup, Audio Layer 3) players), vehicles, medical devices (e.g., heartmonitor, blood pressure monitor, etc.), set top boxes, and others.

The above description and the drawings illustrate some embodiments ofthe invention to enable those skilled in the art to practice theembodiments of the invention. Other embodiments may incorporatestructural, logical, electrical, process, and other changes. In thedrawings, like features or like numerals describe substantially similarfeatures throughout the several views. Examples merely typify possiblevariations. Portions and features of some embodiments may be includedin, or substituted for, those of others. Many other embodiments will beapparent to those of skill in the art upon reading and understanding theabove description. Therefore, the scope of various embodiments of theinvention is determined by the appended claims, along with the fullrange of equivalents to which such claims are entitled.

The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring anabstract that will allow the reader to quickly ascertain the nature andgist of the technical disclosure. The Abstract is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims.

1. An apparatus comprising: a memory element configured to storeinformation; and an access component configured to allow conduction ofcurrent through the memory element when a first voltage difference in afirst direction across the memory element and the access componentexceeds a first voltage value and to prevent conduction of currentthrough the memory element when a second voltage difference in a seconddirection across the memory element and the access component exceeds asecond voltage value, wherein the access component includes a materialexcluding silicon, and, wherein the access component includes aconduction path formed by one of ions and vacancies of the material ofthe access component when the first voltage difference exceeds the firstvoltage value.
 2. The apparatus of claim 1, wherein a current versusvoltage characteristics of the access component includes a hysteresisswitching region between the first and second voltage values.
 3. Theapparatus of claim 1, wherein the first value is greater than the secondvalue.
 4. The apparatus of claim 1, wherein the conduction path isdiscontinuous when the second voltage difference exceeds the secondvoltage value.
 5. The apparatus of claim 1, wherein the access componentand the memory element have a cylindrical structure.
 6. An apparatuscomprising: a memory element configured to store information, the memoryelement including a unipolar switching memory material; and an accesscomponent coupled in series with the memory element between first andsecond electrodes and configured to allow conduction of current throughthe memory element, the access component including a material excludingsilicon, wherein the material includes a bipolar switching material. 7.The apparatus of claim 6, wherein the bipolar switching materialincludes one of ion conducting chalcogenide, binary metal oxide, andperovskite oxide.
 8. The apparatus of claim 7, wherein the unipolarswitching memory material includes a chalcogenide material.
 9. Theapparatus of claim 7, wherein the ion conducting chalcogenide includes afirst layer of germanium selenide (GeSe), a layer of silver selenide(AgSe), a second layer of germanium selenide (GeSe), a layer of silver,and a third layer of germanium selenide (GeSe).
 10. The apparatus ofclaim 7, wherein the ion conducting chalcogenide includes a first layerof germanium selenide (GeSe), a layer of tin selenide (SnSe), a secondlayer of germanium selenide (GeSe), a layer of silver, and a third layerof germanium selenide (GeSe).
 11. The apparatus of claim 9, wherein thefirst layer of germanium selenide (GeSe) has thickness of about 15nanometers (nm), the layer of silver selenide (AgSe) has a thickness ofabout 47 nm, the second layer of germanium selenide (GeSe) has thicknessof about 15 nm, the layer of silver has a thickness of about 20 nm, andthe third layer of germanium selenide (GeSe) has a thickness of about 10nm.
 12. The apparatus of claim 7, wherein the binary metal oxideincludes one of Hafnium oxide (HfO), Nobium oxide (NbO), aluminum oxide(AlO), tungsten oxide (WO), titantalum oxide (TaO), titanium oxide(TiO), zirconium oxide (ZrO), iron oxide (FeO), and nickel oxide (NiO).13. The apparatus of claim 7, wherein the perovskite oxide includes oneof strontium titanium oxide (SrTiO), strontium zirconium oxide (SrZrO),and barium titanium oxide (BaTiO).
 14. An apparatus comprising: a firstdevice level including a first memory cell coupled between a firstelectrode and a second electrode; and a second device level stacked overthe first device level, the second device level including a secondmemory cell coupled between a third electrode and a fourth electrode,each of the first and second memory cells including a memory element andan access component coupled to the memory element, wherein the memoryelement includes a unipolar switching memory material, and the accesscomponent includes a material excluding silicon, wherein the materialincludes a bipolar switching material.
 15. The apparatus of claim 14further comprising a first conductive line coupled to the firstelectrode, a second conductive line coupled to the fourth electrode, anda third conductive line coupled to the second and third electrodes. 16.The apparatus of claim 15, wherein the first conductive line issubstantially parallel to the second line, and wherein the third line issubstantially perpendicular to the first and second lines.
 17. Theapparatus of claim 15, wherein the first memory cell is configured toconduct current between the first and second electrodes when a voltagevalue of a signal on the first line is greater than a voltage value of asignal on the third line, and wherein the second memory cell isconfigured to conduct current between the third and fourth electrodeswhen a voltage value of a signal on the third line is greater than avoltage value of a signal on the second line.
 18. The apparatus of claim15, wherein the unipolar switching memory material includes a phasechange material.
 19. The apparatus of claim 18, wherein the phase changematerial includes a compound of germanium, antimony, and tellurium. 20.The apparatus of claim 18, wherein the material of the access componentincludes silver-doped germanium selenide (GeSe).
 21. The apparatus ofclaim 18, wherein the material of the access component includessilver-doped germanium sulfide (GeS).
 22. A method comprising: applyinga first signal to create a first voltage difference in a first directionacross a memory element and an access component of a memory cell of thememory device to turn on the access component; and applying a secondsignal to create a second voltage difference in a second directionacross the memory element and the access component to turn off theaccess component, wherein the first voltage difference exceeds a firstvoltage value and the second voltage difference exceeds a second voltagevalue, wherein the access component includes a material excludingsilicon, wherein the material includes a bipolar switching material. 23.The method of claim 22 further comprising: applying an additionalcurrent through the memory element and the access component when theaccess component is turned on to determine a resistance of a material ofthe memory element.
 24. The method of claim 22 further comprising:applying an additional current through the memory element and the accesscomponent when the access component is turned on to change a resistanceof a material of the memory element from a first resistance value to asecond resistance value.
 25. A method comprising: forming a memoryelement of a memory cell; and forming an access component to allowconduction of current through the memory element when a first voltagedifference in a first direction across the memory element and the accesscomponent exceeds a first voltage value and to prevent conduction ofcurrent through the memory element when a second voltage difference in asecond direction across the memory element and the access componentexceeds a second voltage value, wherein the access component including amaterial excluding silicon, wherein forming the memory element and theaccess component includes: depositing multiple layers of materials overan electrode of the memory cell; and removing a portion of each layer ofthe multiple layers to form a pillar coupling to the electrode, thememory element being a first part of the pillar and the access componentbeing a second part of the pillar.
 26. The method of claim 25, whereinthe pillar includes a cross-section with a substantially circular shape.27. The method of claim 25, wherein depositing the multiple layers ofmaterials includes depositing a unipolar switching memory materialcontacting the electrode, and depositing a bipolar switching materialover the unipolar switching memory material.
 28. The method of claim 27,wherein the unipolar switching memory material includes a phase changematerial.
 29. The method of claim 28, wherein the bipolar switchingmaterial includes one of ion conducting chalcogenide, binary metaloxide, and perovskite oxide.
 30. The method of claim 25, wherein a thirdpart of the pillar forms an additional electrode of the memory cell, andwherein the memory element and the access component are between theelectrode and the additional electrode.
 31. The method of claim 25further comprising: depositing multiple additional layers of materialsover the pillar; and removing a portion of each layer of the multipleadditional layers to form an additional pillar, the additional pillarincluding a first part forming a memory element of an additional memorycell and a second part forming an access component of the additionalmemory cell.
 32. The method of claim 31 further comprising: forming anadditional electrode over the pillar before depositing the multipleadditional layers over the pillar, the additional electrode beingdirectly contacting the pillar and directly contacting the additionalpillar.